Flip chip on standard lead frame: laminate performance at a lower cost

Abstract

Flip Chip (FC) technology has been used for the last 30 years for high density, thermally challenging, high-speed IC packaging requirements. Originally done on very expensive ceramic substrates for mainframe computers, the technology was given a great boost forward by the implementation of the lower cost laminate-based PBGA technology. While laminate technology provided a significant cost, weight, and lead-time reduction in packaging technology, that helped revolutionize the PC and laptop computer markets, this still left a significant portion of the IC using marketplace unable to afford the benefits of FC technology. This paper discusses the advent of FC technology in low cost lead frame based IC packages for wireless, automotive and consumer electronic applications. By selectively engineering the die layout and by applying new and improved redistribution, bumping, and assembly technologies it is possible to take non-pad limited die and redistribute its I/O to a 200, 300, or 400 micron pitch and use the existing conventional lead frame IC packages infrastructure. The abbreviated assembly process and the re-use of existing tooling allows for a significant reduction in overall tooling charges. These new IC packages while having the same outward appearance, have a significant improvement in moisture sensitivity level (MSL), electrical performance, and in many instances where the die can be exposed, improved thermal performance at a cost significantly below that of laminate based FC technology.