Drift induced rigid current shift in Ge-Rich GST Phase Change Memories in Low Resistance State

Abstract

Ge-Rich GST based Phase Change Memories (PCMs) represent a valid candidate for embedded non-volatile storage due to high-temperature stability, which enables data retention compatible with automotive applications and data integrity in case of soldering reflow stress. Howeover, Ge-Rich GST based PCMs are affected by resistance drift both for cells programmed in the high-resistance state (HRS) and for cells programmed in the low-resistance state (LRS). Our experimental investigation, carried out on a population of 500k cells in a memory array, showed that the variation over time of the LRS cell current is substantially constant for all the cells in the array, regardless of the value of the cell current (and, hence, of the cell resistance) measured just after programming, which results in a rigid cell current shift. Starting from the obtained experimental results, we derived an expression to calculate the drift coefficient in LRS cells as a function of their initial resistance.