Double patterning with dual hard mask for 28-nm node devices and below

Abstract

A double patterning process resulting in amorphous silicon (a-Si) gate lines with a thickness of 80 nm and a lateral critical dimension <30 nm is reported. A full stack for a double patterning approach for etch transfer down to an Si layer, including a hard mask (HM) in which the line and cut patterning are performed, is presented. The importance of the HM in the success or failure of the exercise is evidenced. Once the suitable HM has been selected, the etch chemistry is shown to have a significant impact on the line width roughness (LWR) of the gate. Ultimately, remarkably low LWR could be achieved on gates exhibiting a straight profile. All the results shown in this paper have been obtained on 300-mm wafers.