The Improvement of Poly-Si Gate Line Width Roughness

Abstract

LWR (line width roughness) is normally defined as the 3 sigma of critical dimension (CD) variation along a segment of a line. As CDs of semiconductor devices continue to be scaled down, LWR, the looming critical index, needs to be well controlled within 8% of gate line CD for advanced logic technology nodes as ITRS states. In this contribution, we mainly focused on the gate etch solution to reduce post-gate etch LWR including PPT (pre-plasma treatment), post-Barc (bottom anti-reflective coating) treatment (cure) and plasma induced polymer formation (coating). Besides, we also leveraged the uniform design experiment (UDE) to investigate the impact of Barc/Cure/Darc (dielectric anti-reflective coating) open steps on LWR and identified the optimal Barc/Darc condition among 25 UDE pi-runs. Finally, we obtained the optimal gate etch condition which achieved 2.8nm (the strictest CD-SEM algorithm ever reported) overall LWR performance including both low frequency and high frequency components), roughly more than >30% LWR improvement compared to the initial photoresist LWR. As implant has been reported to be the only way to reduce the low frequency LWR for photoresist, LWR improvement from various implant species and doping levels, the side-effects of implantation and its potential contribution to the overall improvement of post-etch LWR are also addressed.