Abstract
This work presents a unique time-efficient and reliable floorplan algorithm DOTFloor (Diffusion Oriented Time-improved Floorplanner), built around a SA (Simulated Annealing) engine and targeted to optimize the peak on-chip temperature along with the traditional design metrics like chip area and wire length. This paper also proposes a novel heat-diffusion based stochastic thermal model called the FATT (Fast Assumption Technique for Temperature) which provides a fast assumption of the degree of hotness during the optimization process. The incorporation of FATT in DOTFloor results in a significant improvement in the run time of the optimization process. Upon experimentation on MCNC (Microelectronics Center of North Carolina) benchmark circuits with the proposed floorplanner, a good optimization in area, wire length metric and peak on-chip temperature with a significant reduction in execution time have been achieved over the existing floorplanning tool, the HotFloorplan.
Highlights
In the realm of thermal management in processors, floorplanning plays a key role at the physical design level of VLSI technology
(b) DOTFloor achieves an average improvement of 4.04% area in the area-aware solutions, 0.38% wire length metric (WLM) in the WLM-aware solutions, 0.16% peak temperature in the temperature-aware solutions respectively over the HotFloorplan tool, considering the case of rotatable macrocell floorplans
(b) DOTFloor has achieved an average improvement of 9.13% area, -2.74% wire length metric (WLM) and 0.38% peak temperature in the optimal floorplan solution composed of rotatable macrocells with respect to the HotFloorplan
Summary
In the realm of thermal management in processors, floorplanning plays a key role at the physical design level of VLSI technology. Authors in [10] present a thermal-aware floorplanner for slicing floorplan by modeling the temperature-dependent wire delay, routing congestion and reliability factors and including the same in addition to the chip area and temperature metrics in the cost function of the HotFloorplan tool. Work presented in [18] reveals a fast fixed outline multilevel floorplanner based on a thermal-aware non-linear model to simultaneously optimize the chip temperature and wire length. Our paper renders the following salient contributions – (i) It presents a unique thermal-aware floorplanner called the DOTFloor (Diffusion Oriented Time-improved Floorplanner), developed around the classical Simulated Annealing (SA) algorithm [24]–[26] to handle slicing floorplan structures composed of fixed as well as rotatable and hard functional-blocks. The inclusion of FATT in the DOTFloor is responsible for the relative improvement in time efficiency for the floorplanner. (iii) It defines a weighted cost function that evaluates the fitness of a floorplan solution and facilitates the adjustment of tradeoffs between the cost metrics for the attainment of the final optimized solution
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