Abstract
VLSI Floor-planning is known to be a NP hard problem. Therefore, most of the EDA tools use heuristic algorithms to solve this problem that yield near optimal solutions. Simulated annealing has been known to produce good results in floor planning. However, the results of simulated annealing can be biased by the initial placement of the modules. In this paper we study the effect of initial placement on the floor planning. The method can be used on slicing and non- slicing floor-plans. The proposed algorithm uses the number of blocks as specified in Microelectronics Centre of North Carolina (MCNC) benchmark circuits. The results are obtained for different configurations of a single floor plan and the best floor-plan is chosen as a near optimal solution.
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