Doping-less Tunnel Field-effect Transistor with a Gate Insulator Stack to Adjust Tunnel Barrier

Abstract

This paper suggests a doping-less TFET that shows high performance in low power circumstances and its electrical characteristics are analyzed. The doping-less TFET’s gate insulator consists of ONO (SiO₂-Si₃N₄-SiO₂) triple dielectric. When programmed, the tunnel barrier is formed by electron charge traps of nitride region. Then, the tunnel barrier is adjusted by trapped electrons in silicon nitride region. Therefore, it is possible to control the electrical characteristics of the device by controlling the number of electrons trapped in the nitride region by adjusting the program time. However, since the device is made of doping-less, the depletion area has increased as the substrate thickness due to the loss of control of the gate. So, the thinner the substrate thickness of the device, the better the efficiency. In the case of thin substrate thickness, TCAD simulation was per-formed by applying a 5 nm of substrate thickness because the thinner the substrate thickness of the device, the more efficient it is. As a result, the proposed device shows low subthreshold swing (SS) of 29.01 ㎷/decade at 0.5 V of V<SUB>DS</SUB> in the transfer curves. Then, the proposed TFET can control the electrical characteristics with program time and can be driven with low power due to having a low SS.