Distributed Indication in LUT-Based Asynchronous Logic

Abstract

The method of indicating asynchronous logic design, targeting Look-Up-Tables (LUTs) is proposed. It produces a dual-rail multi-level network optimized for the speed and area. The optimization is done using the resubstitution. Initially, a single-rail multi-level network is created using ABC script. Then each node is transformed into dual-rail logic. The conditions of the distributed indication are formulated and the procedure is proposed. For the network compact representation and optimization, an extended dual-rail PLA table is used. The resubstitution targeting multi-output logic is formulated and solved as a covering task: the output of the node, whose inputs have been selected for the resubstitution, is split into the set of dichotomies. The set of inputs satisfying formulated target (optimization for the speed or area) are sought to cover the dichotomies. The nodes with zero fan-outs are removed. The set of benchmarks is processed and results are compared. The experiments show, that the method significantly improves results (on average, 18.7% for the speed and 39.3% for the area respectively).