Asynchronous logic design targeting LUTs

Abstract

The conventional approach to logic design targeting LUTs of limited inputs number is oriented on multi-level decomposition. Nowadays reconfigurable chips contain multiple LUTs that can be combined. It implies producing LUT-based structure of various inputs number to match design needs. As a result, a function can be implemented using one-level LUT which increases circuit performance. In the paper, asynchronous dual-rail logic function design targeting LUT of minimal size (number of inputs) is proposed. It is based on conventional Sum-Of-Product terms (SOP) functions what is in contrast to existing methods where Sum-Of-Minterms (SOM) and Disjoint SOP representations are considered. It is shown, that LUT architectural features and delays ensure SOP hazard-free implementation. Although SOP representation reduces LUT size, existing methods and tools producing SOP (for example, Espresso) are primary oriented on product term minimization. In the paper, the method of generating SOP targeting literal number minimization is proposed. Within this method, efforts are focused on literal (rather that product term) minimization. The task is formulated as a unate covering problem. A heuristic algorithm to solve the problem is proposed. Two sets of benchmarks are processed and comparison of SOM and SOP implementations is done. Using our method, improvement w.r.t. LUT size is achieved.