Distributed arithmetic based non recursive filter for high throughput and low power applications

Abstract

The proposed work demonstrates a design of adaptive nonrecursive filter design based on distributed arithmetic technique. First, the efficient pipelined distributed arithmetic technique has been proposed here, it achieves low power and reduced switching activity than the conventional one. Second, to attain high throughput the parallel processing based distributed technique is designed. Analysis has been made between the first and second model experimental result shows pipelined DA technique increasing the speed with reduced switching activity and to achieve better area, parallel processing technique will be the efficient one. The proposed design is simulated in modelsim 6.5b by using VHDL, synthesized in Xilinx ISE 14.2 and implemented in FPGA Spartan-3E.