Abstract
This paper presents the application of discrete event system (DES) techniques to delay fault modeling and analysis. DES is a dynamical system that evolves according to asynchronous occurrence of certain discrete changes, called events. An integrated circuit (chip) may be considered as a discrete event system. DES modeling techniques are used for delay fault analysis of a chip design. This formal analysis technique may help avoid some of the large cost of simulation, DES delay gate models and circuit path delay models are developed as well as algorithms that provide design testability evaluation and robust delay fault test generation.
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