Delay fault analysis using discrete event system approach

Abstract

An important goal of combinational logic design is that all possible delay faults are detectable with a set of robust delay fault tests. Discrete event system (DES) is a dynamical system that evolves according to asynchronous occurrence of certain discrete changes, called events. Any combinational logic circuit can be considered a discrete event system. In this paper, a formal verification method based on DES modeling techniques is developed for delay fault testability analysis. DES logic delay gate models and circuit path delay models are constructed such that this formal verification method evaluates robust delay fault testability and provides robust delay fault test patterns.