Robust delay-fault test generation and synthesis for testability under a standard scan design methodology

Abstract

of the principal reasons that robust delay-fault testing has not been used extensively in industry is that the application of a robust test vector pair to the combinational logic portion of a VLSI sequential circuit requires that the memory elements in the circuit be enhanced scan flipflops, i.e. flipflops that can store, not just one, but two bits of state. This is because an arbitrary vector pair may not be able to be robustly applied to a sequential circuit under a standard scan design methodology. In this paper, we address the problem of test generation for, and the synthesis of, VLSI sequential circuits that are robustly delay-fault testable under a standard scan design methodology. We present synthesis and test results on several real designs. While a high degree of robust delay-fault coverage is desirable, a number of problems are associated with testing robustly in delay fault models. The first problem is creating logic that is highly testable for delay faults. Synthesis for delay-fault test+ bility of Combinational circuits has recently been the subject of extensive investigation (e.g. (15, 9, 161). Practical integrated circuit designs that are completely hazard-free robustly path- delay-fault testable were automatically synthesized using the techniques presented in (5, 31. The work in (5, 31 assumes an enhanced-scan design methodology for the robust application of test vector pairs. Another obstacle to delay-fault testing is the large vector sets required to test each path in a (hazard-free) robust manner (17) (4). This problem is addressed in (15) where a general robust path-delay-fault model is proposed which can potentially significantly reduce the test vector sets. Another alternative is to use delay fault models with a fewer number of faults such as the gate delay fault model. Results presented in (3) show that by using a gate-delay-fault model rather than a path-delay- fault model can reduce the required number of test vectors to a manageable number. A remaining important barrier in the practical use of robust delay-fault testing is that the application of a robust test vector pair to the combinational logic portion of a VLSI sequential circuit may require that the memory elements in the circuit be enhanced scan flipflops, i.e. flip-flops that can store, not just one, but two bits of state. This is because an arbitrary vector pair may not be able to be robustly applied to a sequential circuit under a non-scan or a standard scan design methodology. The use of an enhanced scan latch imposes a costly area penalty that is prohibitively expensive for many circuit designs. In this paper, we address the problem of test generation for, and the synthesis of, VLSI sequential circuits that are robustly delay-