A Partial Enhanced-Scan Approach to Robust Delay-Fault Test Generation for Sequential Circuits

Abstract

The increasing demand for quality in VLSI designs and fabrication processes is motivating test engineers to test circuits in more comprehensive fault models such as transistor stuckopen faults and delay faults. The detection of delay faults requires the application of a vector pair, and the circuit has to be clocked at speed after the application of each vector. Arbitrary vector pairs cannot always be applied at speed to a sequential circuit implemented with standard scan design. In order to apply an arbitrary vector pair, the circuit may have to be implemented with enhanced-scan flip-flops that can store two bits of state. Using these flip-flops can result in a significant area overhead. In this paper we address the problem of robust path-delayfault test generation for sequential circuits by using a partial1 enhanced-scan/standard-scan approach and by using the notion of scan shifting. Vector pairs that can be obtained by single-bit shifts can be applied at speed under standard scan. We first give an algorithm to determine an eficient ordering of the flip-flops in the scan chain using the information derived from running a delay test generator on the circuit. Given an ordering of the flip-flops, we give an optimization algorithm that attempts to minimize the number of flip-flops to be made enhanced-scan so as to obtain the required level of delay-fault coverage. We show how the test vector sets derived using our test generator can be compacted by solving a clique covering problem. We present test generation, flip-flop ordering, flip-flop selection and test set compaction results on large benchmark circuits.