Abstract
The authors consider the effects of single event upsets (SEUs) on digital systems, and show techniques for designing reliable systems with current levels of SEU protection. Three main systems are discussed: main memory, logic, and cache memory. A design for the main and cache memory subsystems that are SEU protected is also described. With SEU defined in bit days p, and using single error correction, it is shown that for all subsystems considered, an effective upset rate which is proportional to the product of p/sup 2/ and the time between corrections, or scrub time, can be obtained. Data for memory chip size and performance derived from the gallium-arsenide (GaAs) pilot lines funded by the Defense Advanced Research Projects Agency (DARPA) throughout the 1980s are used. >
Sign-in/Register to access full text options 
Free) 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a call
