FAULT AND RELIABILITY ANALYSIS OF CARBON NANO TUBE FET SRAM IN THE PRESENCE OF SINGLE EVENT UPSET

Rajalakshmi Rajalakshmi

doi:10.3844/ajassp.2014.1343.1350

Abstract

Carbon nano tube devices are considered as a better replacement for CMOS technology nowadays due to its decreased sizing and increased performance. Resisti ve open and bridging faults play vital role in the dynamic fault analysis. These faults are important since th e number of interconnects have increased. In this s tudy we discuss the effect of open and bridging defects alo ng with the variation of CNTFET parameters in the presence of Single Event Upsets (SEU). This helps us to analyse and have good comparison of CNTFET and CMOS SRAM faults in the presence of SEU. The analysis of thes e faults in the presence of SEU helps us to develop new efficient techniques to improve the performance. Pr esence of single event upset in the presence of the se defects was analysed. The fault introduction in CNTFET SRAM showed different fault types for corresponding resistance values. The impact of resistive open def ects and bridging defects on CNTFET SRAM in presence of SEU is estimated for different values of resistance s compared close to CMOS SRAM.

Highlights

Analyse CNTFET SRAM cells behaviour in the presence of resistive open defects under Single Event Upsets (SEU) radiation and to do the
Previous works include the analysis of resistive open due to some external influences. These errors and influences are more prominent in NANO scale devices defects, resistive open defects in the presence of SEU, resistive bridging defects and their impact on error rate than in CMOS devices
The impact of single event upset is studied for CNTFET SRAM

Summary

Introduction

Analyse CNTFET SRAM cells behaviour in the presence of resistive open defects under SEU radiation and to do the. Previous works include the analysis of resistive open due to some external influences. These errors and influences are more prominent in NANO scale devices defects, resistive open defects in the presence of SEU, resistive bridging defects and their impact on error rate than in CMOS devices. This study analyses the impact of resistive open defects, bridging defects and the impact of alpha and neutron particles on these defects. This study concludes the various faults in the presence of resistive open defects and their impact with respect to single Event upsets. The paper discusses the bridging defects in nano scales and has given good comparison regarding faults with different technology

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Conclusion