Abstract
This paper presents a new structure of Dielectric Separated Independent Gates Junctionless Transistor (DSIG-JLT) with four independent gates. The proposed DSIG-JLT is used to implement area and power efficient digital circuits by optimizing structure of the device and circuit level logic. This paper includes the modeling, simulation and design overview of DSIG-JLT to analyze the behavior of the device. Physics based analytical model explains the working principle of DSIG-JLT. It has four independent gates which are electrically controlled in multiple ways to realize full functionality of NOT, NAND, NOR Gate and Half-adder circuit. ATLAS 3-D device simulator is used to verify the developed model.
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