Die Embedding Challenges for EMIB Advanced Packaging Technology

Abstract

Intel's Embedded Multi-die Interconnect Bridge (EMIB) technology is an advanced, cost-effective approach to in-package high density interconnects of heterogeneous chips, providing high density I/O, and controlled electrical interconnect paths between multiple dice in a package. This technology uses local silicon bridges to host ultrafine line / space structures for die-to-die interconnect communications and opens avenues for heterogeneous chip integration applications. In EMIB package architecture, a silicon bridge die is embedded into an organic substrate, encapsulated with dielectric materials, and connected to external layers of package substrate through semi additive substrate build-up processes at the panel level. Many bridge dice can be embedded as part of the high-density interconnect package substrate fabrication process. Afterwards, logic or heterogeneous dice (Chiplets of various nodes / sources, HBMs, IO tiles, etc.) are bonded to EMIB substrates through assembly process, with EMIB bridges serving as a high-bandwidth, low-latency, and low-power solution for die-to-die communications, thereby enabling a low-cost, highperformance in-package heterogeneous chip integration solution. Simply put, EMIB employs a silicon piece that hosts ultrafine line / space structures, fabricated with silicon far-backend technology, but out of Intel's high-density interconnect package substrate manufacturing infrastructures and capabilities. One of the key elements of EMIB advanced packaging technology is to embed the EMIB bridge dice reliably during the substrate fabrication process. As such, an overview of the general technical challenges associated with panel level EMIB die embedding will be presented in this paper as compared to the industry standard wafer level packaging (WLP) die embedding process.