Abstract

In recent years, subthreshold operation has gained a lot of attention due to ultra low-power consumption in applications requiring low to medium performance. It has also been shown that by optimizing the device structure, power consumption of digital subthreshold logic can be further minimized while improving its performance. Therefore, subthreshold circuit design is very promising for future ultra low-energy sensor applications as well as high-performance parallel processing. This paper deals with various device and circuit design challenges associated with the state of the art in optimal digital subthreshold circuit design and reviews device design methodologies and circuit topologies for optimal digital subthreshold operation. This paper identifies the suitable candidates for subthreshold operation at device and circuit levels for optimal subthreshold circuit design and provides an effective roadmap for digital designers interested to work with ultra low-power applications.

Highlights

  • In digital VLSI system design space, considerable attention has been given to the design of high-performance microprocessors

  • Digital computation using subthreshold leakage current has gained a wide interest in recent years to achieve ultralow-power consumptions in portable computing devices

  • As supply voltage continues to scale with each new generation of CMOS technology, Sub-threshold design is an inevitable choice in the semi-conductor road map for achieving ultra low-power consumption

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Summary

Introduction

In digital VLSI system design space, considerable attention has been given to the design of high-performance microprocessors. Design of digital subthreshold logic was investigated with transistors operated in the subthreshold region (supply voltage (Vdd) less than the threshold voltage (Vth)) of the transistor) [1,2,3,4] In such a technique the subthreshold leakage current of the device is used for necessary computation. Digital computation using subthreshold leakage current has gained a wide interest in recent years to achieve ultralow-power consumptions in portable computing devices. Both logic and memory circuits have been extensively studied with design consideration at various levels of abstraction.

Scope of Subthreshold Operation for Ultralow Power Applications
Device-Level Optimization Methodologies for Subthreshold Operation
DGMOS Devices with Optimum Longer Channel
Logic Families for Subthreshold Operation
Findings
Conclusions
Full Text
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