Development of less expensive process technologies for three-dimensional chip stacking with through-vias

Abstract

Three-dimensional chip stacking with through-vias is a very promising technology in semiconductor system development. A major problem of this technology is the cost. We analyzed the costs of the fabrication process and identified the three processes of Cu plating, Cu-CMP, and back surface bumps as the high-cost processes. To address these problems, we studied the processes and the stacking structure to improve the productivity. The plating time for Cu plating was reduced by up to 1 hour by optimizing the plating fluid composition and the oxygen bubbling of the plating fluid. In Cu-CMP, 9-µm-thick Cu was polished for 8.7 minutes by using high-speed polishing slurry and the softlanding process. We evaluated a structure where the back surface bumps were removed, and the front surface Cu bumps were directly connected by Cu through-vias and Sn-Ag. We verified the reliability for up to 1000 temperature cycles of this structure which uses a low thermal expansion resin as the adhesive in two-step sealing. From these results, a substantial reduction in the cost of the three-dimensional chip stacking with through-vias has become possible. © 2005 Wiley Periodicals, Inc. Electron Comm Jpn Pt 2, 88(7): 50–60, 2005; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/ecjb.20150