Development of Interface Model and Design of Compensator to Overcome Delay Response in a PHIL Setup for Evaluating a Grid-Connected Power Electronic DUT

Abstract

The power hardware in the loop (PHIL) is an attractive way of performing various studies for testing a non-linear power electronic converter in laboratory scale and yet get a result that resembles an actual like scenario. This approach, however promising, suffers from various stability problems arising due to the interface between the hardware and software environment required to create a PHIL. This article presents a thorough analysis of the stability problem in PHIL by individually studying the interface device that forms the ideal transformer method (ITM) interface. The model of the ITM interface is developed and verified experimentally using a frequency sweep approach. The developed model can serve as a tool to understand the factors affecting the stability in a PHIL set up. Utilizing the developed model, this article proposes a Smith predictor (SP) compensator that eliminates the effect of delay in the closed loop response of the system. The SP compensator is designed and implemented in a real time digital simulator platform and the performance of the compensator is verified through various experiments. A case study of a compensator employed resistor divider network is presented to validate a stable PHIL, both theoretically and experimentally. Further, the proposed compensator is tested to evaluate a 250 W grid connected photovoltaic inverter in a PHIL.