Validation of an impedance measurement by deliberate destabilization of a power hardware in the loop setup

Abstract

The inverter impedance estimation is an integral part of the practical application of the impedance-based stability assessment. Now the question arises about the validity of the estimated impedances, due to disturbances in the measurement and the estimation error of the system identification algorithm. In this paper, a practical approach to determine the validity of the estimated impedance by determining the stability limits of a power hardware in the loop (PHIL) setup is proposed. For this purpose, the dynamic behaviour of all components in the PHIL-setup is determined. To confirm the functionality of the proposed method, it is used to validate the estimated impedance of a Cinergia EL15-AC&DC dynamic load in the laboratory.