Abstract

SRAM is vulnerable to device-to-device variation (DDV), since it uses minimum-sized devices and requires device matching. In addition to the as-fabricated DDV at time-zero, aging induces a time-dependent DDV (TDDV). Bias temperature instability (BTI) is a dominant aging process. A number of techniques have been developed to characterize the BTI, including the conventional pulse-(I) -(V) , random telegraph noises, time-dependent defect spectroscopy, and TDDV accounting for the within-device fluctuation. These techniques, however, cannot be directly applied to SRAM, because their test conditions do not comply with typical SRAM operation. The central objective of this paper is to develop a technique suitable for characterizing both the negative BTI (NBTI) and positive BTI (PBTI) in SRAM. The key issues addressed include the SRAM relevant sensing Vg, measurement delay, capturing the upper envelope of degradation, sampling rate, and measurement time window. The differences between NBTI and PBTI are highlighted. The impact of NBTI and PBTI on the cell-level performance is assessed by simulation, based on experimental results obtained from individual devices. The simulation results show that, for a given static noise margin, test conditions have a significant effect on the minimum operation bias.

Highlights

  • SRAM can occupy over 50% of the space for system-on-a-chip products, forcing it to use the minimum-sized devices

  • A number of techniques have been developed to characterize the Bias temperature instability (BTI) and the time-dependent DDV (TDDV), including the conventional pulse IV [25,26], random telegraph noises (RTN) [11,12,13, 27,28,29], time dependent defect spectroscopy (TDDS) [8], and TDDV accounting for the within-a-device fluctuation (TVF) [14,15]

  • After 1000 sec stress, the average of negative bias temperature instability (NBTI) is 5 times of that of positive bias temperature instability (PBTI). The difference in their standard deviation, is smaller. This leads to a higher σ/μ for PBTI (Fig. 15(c)), indicating the device-to-device variation is relatively larger for PBTI of nMOSFETs

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Summary

INTRODUCTION

SRAM can occupy over 50% of the space for system-on-a-chip products, forcing it to use the minimum-sized devices. A number of techniques have been developed to characterize the BTI and the TDDV, including the conventional pulse IV [25,26], random telegraph noises (RTN) [11,12,13, 27,28,29], time dependent defect spectroscopy (TDDS) [8], and TDDV accounting for the within-a-device fluctuation (TVF) [14,15] The impact of BTI-induced TDDV on the static noise margin (SNM) and the minimum operation voltage of SRAM will be simulated and their sensitivity to test conditions will be highlighted

DEVICES AND EXPERIMENTS
SHORTCOMINGS OF EXISTING TECHNIQUES
Typical operation conditions of SRAM
Shortcomings of existing techniques
CHARACTERIZE BTIS-INDUCED TDDV FOR SRAM
Measuring a single device AC or DC stress
NBTI-induced TDDV
PBTI-induced TDDV
Impact on SRAM
Findings
CONCLUSIONS
Full Text
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