Abstract
Negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI) are critical circuit reliability issues in highly scaled CMOS technologies. In this paper, we analyze the impacts of NBTI and PBTI on SRAM VMIN, and present a design solution for mitigating the impact of NBTI and PBTI on SRAM VMIN. Two different types of SRAM VMIN (SNM-limited VMIN and time-limited VMIN) are explained. Simulation results show that SNM-limited VMIN is more sensitive to NBTI while time-limited VMIN is more prone to suffer from PBTI effect. The proposed NBTI/PBTI-aware control of wordline pulse width and woldline voltage improves cell stability, and mitigates the VMIN degradation induced by NBTI/PBTI.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callMore From: JSTS:Journal of Semiconductor Technology and Science
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
