Deterministic Digital Calibration of 1.5 bits/stage Pipelined ADCs by Direct Extraction of Calibration Coefficients

Abstract

This paper proposes a novel foreground digital calibration technique for 1.5 bits/stage pipeline ADCs to calibrate ADC errors due to capacitor mismatch and finite opamp gain. The proposed algorithm directly extracts the weights with which the digital raw code of the pipelined ADC has to be multiplied, with minimal digital operations. Unlike other foreground calibration techniques, the proposed technique does not require forcing the inputs and outputs of the intermediate stages to be calibrated. A 1.5 bits/stage, 12 stage ADC with the four MSB stages calibrated is demonstrated. After calibration, the ADC achieves SNDR of 62 dB at input frequency equal to one third the sampling frequency and 71 dB at lower input frequencies, and SFDR of 64 dB at input frequency equal to one third the sampling frequency and 75 dB at lower input frequencies. The INL and DNL of the calibrated ADC lie below 0.65 LSB and 0.3 LSB, respectively.