An efficient calibration technique for pipeline ADC

Abstract

Capacitor mismatch and finite op-amp gain are two main error sources for high-resolution pipelined ADCs. This paper presents a high-efficiency digital calibration technique for multi-bit/stage pipeline ADCs. Firstly, capacitor mismatch in multi-bit stage is calibrated in foreground due to its stability to environment. And the mismatching information between different capacitors is memorized. Secondly, the finite op-amp gain is calibrated in background due to its sensitivity to environment. Only one step of the multi-bit DAC needs to be tracked, and the others can be calculated out at a much lower frequency, by the aid of the memorized mismatching information. In this way, the presented technique decreases switching activity of the digital calibration circuit and thus is efficient in power dissipation. For verification, a 14-bit 250-MS/s pipelined ADC is fabricated in a standard 1.8V 180nm CMOS process. Simulation results show that the calibration improves the ADC SNDR and SFDR from 61.57 dB and 67.77 dB to 85.49 dB and 100.86 dB respectively.