Determination of DC equivalent hot carrier stress times in scaled CMOS devices using novel AC stress methodology

Abstract

A new AC hot carrier injection (HCI) test methodology replicating the switching in digital CMOS circuits is introduced to correlate HCI in discrete scaled CMOS devices to HCI in logic circuits. This technique allows us to demonstrate that the historic 50× reduction for definition of DC HCI lifetime targets for mid-Vg stress in scaled devices should be uplifted to 1000× based on the correlation with RO degradation for poly-Si/SiON and 14 nm FinFET data. This brings significant HCI relief for device optimization in scaled technology nodes.