Abstract
Application-Specific Instruction-Set Processors (ASIPs) have established their processing power in the embedded systems. Since energy efficiency is one of the most important challenges in this area, coarse-grained reconfigurable arrays (CGRAs) have been used in many different domains. The exclusive program execution model of the CGRAs is the key to their energy efficiency but it has some major costs. The context-switching network (CSN) is responsible for handling this unique program execution model and is also one of the most energy-hungry parts of the CGRAs. In this paper, we have proposed a new method to predict important architectural parameters of the CSN of a CGRA, such as the size of the processing elements (PEs), the topology of the CSN, and the number of configuration registers in each PE. The proposed method is based on the high-level code of the input application, and it is used to prune the design space and increase the energy efficiency of the CGRA. Based on our results, not only the size of the design space of the CSN of the CGRA is reduced to 10%, but also its performance and energy efficiency are increased by about 13% and 73%, respectively. The predicted architecture by the proposed method is over 97% closer to the best architecture of the exhaustive searching for the design space.
Highlights
The complexity of software applications grew exponentially in the last decades
Many different architectures were proposed to improve the performance of the process-intensive part of the application, such as custom instructions extraction [5], using field-programmable gate arrays (FPGAs) or coarsegrained reconfigurable arrays (CGRAs) as a coprocessor [1] or using a graphics processing unit (GPU) to parallelize the loops [1]
Based on the history of the FPGA- or GPU-based Application-Specific Instruction-Set Processors (ASIPs) processors, in this paper, we have focused on the CGRA-based ASIPs
Summary
The complexity of software applications grew exponentially in the last decades. Based on the wide range of those application domains, designing an energyefficient and high-performance general-purpose processor is out of the question. A lot of different processing architectures have been presented to increase both the processing and the energy efficiency of processing platforms. Application-Specific Instruction-Set Processors (ASIPs) are one of the most efficient processing platforms that are used in many different application domains, such as numerical and scientific computing, digital signal processing, data security, artificial intelligence, etc. ASIP processors, by reducing the energy consumption and execution time of that part, optimize the performance of their processing platforms. Many different architectures were proposed to improve the performance of the process-intensive part of the application, such as custom instructions extraction [5], using field-programmable gate arrays (FPGAs) or coarsegrained reconfigurable arrays (CGRAs) as a coprocessor [1] or using a graphics processing unit (GPU) to parallelize the loops [1]. CGRAs established their power in both highperformance and low-power domains [1, 6]
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