Designing with FinFETs and Process Variation Impact

Abstract

Scaled planar transistor devices present significant increases of the leakage current exacerbated by process variations, which limits the performance of some electronic applications. FinFET technology has been adopted starting 22 nm technology node for high-performance and power-efficient applications. This chapter introduces FinFET devices. The fabrication steps for making fins and middle-of-line (MOL) local interconnects are described. Design issues unique to FinFET technology are discussed. A step-by-step procedure to create the layout of an inverter cell is presented. The main sources of process variations in FinFET technology are analyzed, and their impact on the delay performance of logic cells is discussed. The computing of the delay variance (standard deviation) of an inverter gate based on FinFET technology is presented. A hand-by-hand example of computing the delay of a single logic cell is presented.