Analysis of 6 T SRAM cell in sub-45 nm CMOS and FinFET technologies

Abstract

The semiconductor industry is exploring technology scaling to pursuit the Moore's Law. The actual processors operation frequency grows the need for fast memories. Nowadays, SRAM cells occupy a considerable area in VLSI designs. Several challenges follow this performance improvement achieved at each new technology node. The Process, Voltage, and Temperature (PVT) variability, aging effects due to BTI influence and radiation-induced Single-Event Upset (SEU) are three relevant issues on the SRAM nanometer design. The main contribution of this work is to present a panorama of these effects on SRAM as technology scaling. The most frequently used SRAM cell, the 6 T, is evaluated from 45 nm to 7 nm bulk CMOS and FinFET technologies. Results observed the effects on delay, power, and noise margins, showing that process variability can introduce up to 100% of power deviation. Read Static Noise Margin (RSNM) presents about 20% of deviation under process variability and the cell noise robustness is reduced dramatically in worst cases. FinFET technology and high-performance models show more robustness against radiation. SRAM cells with low-power devices demonstrated more sensitive to delay degradation due to aging effects.