Abstract

In this paper, we present a reverse conversion from a two-stage Residue Number System (RNS) to a Binary Number System (BNS) with a special set of level 1 modules {2 α1, 2 α2 − 1, …, 2αn − 1} and level 2 modules {2 β1, 2 β2 − 1, …, 2 β k − 1}. The proposed method is based on the Chinese Remainder Theorem (CRT) with fractions and using a calculation method that uses constant multiplications to speed up calculations. This article discusses the simulation of FPGA reverse conversion to a two-stage RNS using the proposed method and the standard CRT using adders, their comparison of latency and hardware costs.

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