Abstract
We are considering the use of a two-stage Residue number system (RNS) in data transmission systems with a special set of modules {2l1, 2l2, 2l3,…, 2lp − 1}. We propose the forward converter with such type of RNS and demonstrate its advantage in hardware costs and delay. This article discusses the FPGA simulation of a forward conversion circuit to a two-stage RNS using adders and the standard modulo function and their comparison in terms of delay and hardware costs.
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