Residue-to-Binary Converters for High-speed Digital Signal Processing

Abstract

The residue number system (RNS) provides an attractive alternative to traditional weighted number systems for high speed digital signal processing (DSP) and communication applications. To interface with the digital system, where the binary numbers are employed, the RNS-based processors require the conversions between binary form to the residue representation. The residue to binary converters based on the form {2 n, 2n - 1, 2n + 1} have been widely used in RNS architectures, as they offer efficient circuits in AT2 sense. Taking the advantages of area-time efficiency for the modulo 2n circuits, an alternative conversion algorithm for the moduli set {22n 2n - 1, 2n + 1} has been proposed, in which the dynamic range is increased from 3n bits to 4n bits with virtually the same hardware cost and no delay time. This paper further extends the design concept for any arbitrary moduli sets {2pn, 2n - 1, 2n+1}, p is any positive integer, with the dynamic range of(p+2)n bits. This study concludes that the hardware cost and delay time for the converters with p = 2r - 1 and p = 2r, r is any positive integer, are virtually the same