VLSI implementation of residue-to-binary converters for digital signal processing

Abstract

The residue number system (RNS) provides an attractive alternative to traditional weighted number systems for high speed digital signal processing (DSP) and communication applications. To interface with the digital system, where the binary numbers are employed, the RNS-based processors require the conversions between binary form to the residue representation. This paper presents a simple conversion algorithm and hardware implementation for any arbitrary moduli sets {2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">kn</sup> ,2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</sup> -1,2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</sup> +1}, where k is a positive integer. The converter hardware includes nothing but (2n) converting units, where each unit is comprised of a 1-bit FA (full adder), a 2-to-1 MUX (multiplexer), and two latches. Experimental results show that, for n=6 and k=2, the converter takes only an area of 16,968 um with a delay of 14.20 ns, and, for n=8 and k=4, the area is 22,624 um <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> with a delay of 19.54 ns, where the TSMC 0.18 um 1P6M process were employed. Both area and speed performances are significant.