Design of Ternary D-latch Using Graphene Nanoribbon Field Effect Transistor

Abstract

In this paper, the ternary D-latch design using Graphene Nanoribbon FETs (GNRFETs) is presented. The three valued logic (i.e., ternary logic) design is a best alternate solution to the existing binary logic as it provides smaller interconnects, faster computations and smaller chip area. Therefore, the design can allows the energy efficient, low-complex and high-speed circuits in modern digital design. The threshold voltage of the GNRFETs is varied by the graphene width, which depends on the number of dimer lines. The ternary D-latch proposed in our work is implemented utilizing the basic ternary logic designs such as negative and standard inverters and NAND gates. The simulations are carried out using HSPICE simulation tool. It has been observed that the ternary D-latch functioning is correctly implemented using the proposed circuit with GNRFETs.