Design of Single Poly Flash Memory Cell with Power Reduction Technique at Program Mode in 65nm CMOS Process

Abstract

This paper focuses on the bit lines in the design of a single-poly flash memory cell during program operation. A conventional flash memory cell uses a floating gate transistor where an extra layer is added between the gate and substrate of the standard MOSFET. This incurs additional process step during fabrication, increasing the cost of the design. The single poly embedded flash memory cell is quite an attractive solution for non-volatile memory applications since it doesn't require any additional process steps. A 5T single-poly flash memory cell was implemented under TSMC 65nm CMOS Process. During program mode of a single-poly flash memory, all the pull-up PMOS of every single cell are turned on even if some of the cells are not to be programmed, causing a short path between the source and ground thus generating static power dissipation. In this paper, power gating technique was being applied to the bit lines. The size of the PMOS were taken for both design and it was found out that in power-gated, the size of the PMOS didn't really affect the power dissipated. The results from comparing each design showed that with power gating method, the static power dissipation was transformed into dynamic power dissipation, reducing power consumption by about 80%. The cell's dimensions are 14.015 µm x 1.930 µm, achieving an area of 27.05 µm2.