Design of Power Gated True Single-Phase-Clocked Flip-Flop

Abstract

In low-voltage functions, power optimization is critical. This paper shows how to make a low-power Data -Flip flop circuit with header power gating. The architecture's main purpose is to investigate D Flip flop power dissipation in the conceptual design style. Tanner EDA is used to carry out the planned design. The simulation results reveal that using power gating, our suggested cell consumes significantly less energy.