Abstract
Single event upset type of soft error caused by the ionizing radiation is a key constraint for reliable memory design. To correct soft errors in memories, single error correction (SEC) codes are generally used. However the use of multiple bits error correcting codes in memory is limited due to higher decoding complexity. Orthogonal Latin Square (OLS) codes are a type of one-step majority logic decodable (OS-MLD) codes which have been used for memory system. These codes require more number of parity check bits and larger area compare to Hamming and Hsiao codes, when error correction capability exceeds by two. In this paper, a scheme for H-matrix construction of SEC-OLS code has been introduced. The architectures of proposed and existing codes are synthesized on ASIC platform. The synthesis results show that proposed codec is power efficient (highest improvement 7.63%) compared to the existing schemes without increasing area.
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