Abstract
A 3 CNFETs and 2 memristors-based half-select disturbance free 3T2R resistive RAM (RRAM) cell is proposed in this paper. While the two memristors act as the nonvolatile memory elements, CNFETs are employed as high-performance switches. The proposed cell is capable of implementing bit-interleaving architecture and various error correction coding (ECC) schemes can be applied to mitigate soft-errors. The 3T2R cell has been compared with the standard 6T SRAM (S6T) and 2T2R cells. At a supply voltage of 2 V, the 3T2R cell exhibits $7.24\times $ shorter write delay ( ${T} _{\text {WA}}$ ) and $2.89\times $ lower variability in ${T} _{\text {WA}}$ than that of 2T2R. Moreover, it exhibits $5.08\times /4.33\times $ lower variability in ${T} _{\text {RA}}$ and $1.46\times 10^{7}\times /2.07\times $ lower hold power ( ${H} _{\text {PWR}}$ ) dissipation than that of S6T/ 2T2R at ${V} _{\text {DD}} = 2$ V. In addition, it exhibits tolerance to variations in ${V} _{\text {th}}$ of memristor while being immune to resistance-state drift and random telegraph noise (RTN)-induced instabilities during the read operation. The vastly superior characteristics of CNFET devices over MOSFETs, in combination with memristor technology, leads to such appreciable improvement in design metrics of the proposed design.
Highlights
The temporary and permanent data storage requirements of any information processing unit have been accomplished by MOSFET-based memories like DRAM, SRAM and flash memory
That a TiO2-based physical implementation of the device was made possible by HP labs in 2008 [6]. Such metal oxide based resistive switching memory element can be used in resistive random access memory (RRAM) due to its simple composition, low cost and compatibility with CMOS technology [7]
MEMRISTOR AND ITS SWITCHING MECHANISM In this work, the Stanford-PKU memristor model [29], which is a SPICE model of RRAM developed based on the conductive filament (CF) evolution model [30], [31], [32] has been employed
Summary
The temporary and permanent data storage requirements of any information processing unit have been accomplished by MOSFET-based memories like DRAM, SRAM and flash memory. Such metal oxide based resistive switching memory element can be used in RRAM due to its simple composition, low cost and compatibility with CMOS technology [7] It exhibits very low power consumption as well as high packing density. To overcome the various limitations faced by 1R RRAM, 1T1R RRAM and 2T2R RRAM cells, we have proposed a half-select disturb free 3T2R RRAM cell for cache memory application in this work It consists of 3 CNFET devices, which function as switches during various operations, and 2 memristors, which act as memory elements. The row-based wordline (WL) controls the access transistors nCNFET1 and nCNFET2 while the pCNFET1 is activated by row-based WLB
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