Design of Low Power Signed Multiplier Based on EMBR Techniques

Abstract

Multiplier is the major component for processing of large amount of data in DSP applications. Using different recoding schemes in Fused Add-Multiply (FAM) design for the reduction of power and look up tables. The performances of 8-bit, 12-bit & 16-bit signed multipliers were designed and obtained results are tabulated using Efficient Modified Booth Recoding (EMBR) techniques, which can be used for low power applications.