Design of Low Power and High-Speed 6-Transistors Adiabatic Full Adder

Abstract

AbstractIn the era of technological evolution and advancement, energy is the key element or ingredient of all sorts of development. Most of the electronic goods or appliances are based on a battery-operated system. The portable devices are extensively used in laboratories, offices, and industry and defense items. Long-life battery is the merit and an added advantage of any electronics appliances. Low power dissipation ensures the long duration of the stored energy. The arithmetic circuit is a preliminary element of many computing devices. Minimizing the power dissipation of fundamental arithmetic components such as full adders will severely reduce the power across the high-end electronic system. Thus, adiabatic logic is a promising technology that can generate a power-aware circuit with high switching activity. Hence keeping this condition into consideration, this paper introduces a novel circuit of low power 6-Transistors 1-bit adiabatic full adder circuit. The combination of low power and low transistor count makes the new 6-Transistors adiabatic full adder, an achievable option for an efficient design. This paper presents the design of an adiabatic technology-based full adder in 45 nm technology node. The proposed design outperforms over the existing circuits with an exceptional improvement of 33.3% for transistor count and 76% for power dissipation.KeywordsAdiabaticFull adderPower dissipationDelay