Design of encoder for ternary logic circuits

Abstract

Ternary logic is a promising alternative to conventional binary logic, since it is possible to achieve simplicity and energy efficiency due to the reduced circuit overhead. In this paper a design of ternary arithmetic logic circuits based on Carbon Nanotube Field Effect Transistors (CNFETs) is presented. An encoder is proposed in this paper which can be used in ternary arithmetic circuits. A ternary half adder circuit is designed using the proposed encoder. The proposed design and existing designs are synthesized using Synopsys HSPICE and comparison are drawn for circuit parameters like delay, power etc. Simulation results indicate that the proposed encoder based 1-bit half adder design results in 22% delay reduction, 20% power reduction and 39% power delay product reduction when compared to the existing implementation.