Design of Current Mode MOS Logic for Low-Power Digital Applications

Abstract

Today, the major limitation of designing of high-speed integrated circuits (ICs) with conventional technology is the delay limiting the switching speed of the gates. As evident from already established logic styles like complementary pass transistor logic (CPL), differential cascode voltage swing logic (DCVSL), etc., the circuit exploits the property of noise reduction due to differential inputs. Ideally current mode circuits have constant current gain with no input impedance and finite output impedance. The current gain of the circuit is set to unity as current amplification leads to higher consumption of static power. MOS current mode logic (MCML) is graced with certain advantages which include low level of noise generation, static power dissipation independent of switching activity, low voltage swing, a weak dependence of propagation delay on fan-out load capacitance, lower power dissipation at higher frequencies, etc., out way the few disadvantages such as elaborated design process and increased number of design parameters. In this paper, we present an in-depth study of MCML base approach in which the analysis of low-power applications is performed at the target data rate of 1 Gbps. Work has been done on a standard CMOS technology of 0.18 μm.