Design of MCML Based Logic for Low Power Digital Communication Application

Abstract

Delay reduces the speed of operation in high-speed integrated circuits (ICs). The major disadvantage of conventional CMOS logic is slower operation and higher energy consumption. Current steering logic is utilized by MOS Current Mode Logic (MCML) to direct current to current-output logic that is faster, consumes less energy, and offers lower voltage requirements, lower signal integrity, and lower switching noise. MCML has several advantages, including low noise production, a low static power consumption (unchanged by switching), reduced voltage swing, limited propagation delay in fanout loads because of their capacitance, and lower power dissipation at higher frequencies. Multiplexers and De-multiplexers are the best way of reducing the frequency of on-chip clocks. The popularity of low power and high speed Viterbi decoders increases as communication technology progresses due to its improved battery life and less weight. Despite the tremendous improvement over the last decade, Viterbi decoders' power dissipation remains a challenging issue, and requires more sophisticated solutions. A Viterbi decoder using MOS Current Mode Logic is proposed, which is found to consume less power than other logic styles. Work has been designed in 180 nm standard CMOS technology.