Design of CMOS Transistors to Maximize Circuit FOM Using a Coupled Process and Mixed-Mode Simulation Methodology

Abstract

Calibrated process and device CMOS modules were integrated into a mixed-mode simulation setup to study the circuit figure of merit (FOM). Switching delay from typical two-input NAND, two-input NOR, and inverter circuits built and simulated in the device simulator Dessis, including both intra and intercell capacitances and resistances show strong dependence on the drain-induced barrier lowering and associated short-channel electrostatics. The analysis presented in this letter identifies, for a given set of leakage and process constraints, an optimal gate length (L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</sub> ) that maximizes circuit FOM. The analysis also highlights, for the first time, that the optimal L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g </sub> for maximizing circuit FOM is much longer than that required for maximizing the device performance. The optimal L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</sub> for maximum circuit FOM is determined by a complex tradeoff between reduced capacitance, increased short-channel effect, and reduced mobility