Abstract
The analytical modelling of asymmetric gate stack junctionless dual material surrounding gate (AGSJLDMSG) MOSFET was suggested in this article to enhance hot carrier reliability. The innovative construction is focused on an asymmetric gate stack design that combines two distinct high K dielectrics at the source and drain sides, which dramatically decreases electric field and drain induced barrier lowering (DIBL). A comparative evaluation of short channel effects (SCEs) among this innovative structure and various earlier architectures was performed. Surface potential, electric field, DIBL, subthreshold slop, subthreshold drain current (Id), and transconductance (gm) have all been examined as figure of merit (FOM) measures. The results show that the high K dielectric on the drain side increases immunity to hot carrier generated damage and the analog/RF properties. The ATLAS device simulator was used to run the simulations.
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