Design of clock generation circuitry for high-speed subranging time-interleaved ADCs

Abstract

A clock generation system for a 1GS/s 8-bit subranging time-interleaved analog-to-digital converter (ADC) is introduced. General timing considerations for time-interleaved ADCs are reviewed prior to describing the design methodology for a prototype ADC. This hybrid ADC architecture contains four time-interleaved combined sample-and-hold and capacitive digital-to-analog converter (SHDAC) circuits as front-end sample-and-hold for a flash stage and for a time-interleaved successive approximation stage, which minimizes the errors due to sampling time mismatches between the two stages. The associated clock signal generation techniques that enable this hybrid ADC design approach are presented in this paper, which range from particular non-overlapping clocks and extensive buffering to synchronous resetting for adjusting the order of the clock signals in each time-interleaved channel. The transistor-level and layout-level clock generation circuits were designed and simulated in 130nm CMOS technology, and consume 3.88mW from a 1.2V supply. The standard deviation of the timing skews between time-interleaved channels is less than 1ps based on Monte Carlo simulations. To evaluate the feasibility of the clock generation approach, post-layout simulations were conducted with the interconnected ADC core layout and routed clock generation circuits. The hybrid ADC achieved an effective number of bits (ENOB) of 7.39 with a sampling frequency of 1GHz and an input frequency close to the Nyquist rate.