12-bit, 3GS/s, radiation-hard time-interleaved adc for particle accelerator applications

Abstract

Fast-sampling, radiation-hard analog-to-digital converters (ADCs) are needed in detector readout applications, as well as in many accelerator instrumentation applications, such as beam control applications. This paper discusses a 12-bit, 3 GS/s, 1.9 W time-interleaved ADC design that is suitable for both types of these applications. Jitter in clock signals limits the achievable resolution of current gigasample ADCs. We were able to fully utilize the performance benefits from the newest silicon-germanium (SiGe) fabrication processes in the design of an ultralow-jitter front-end sampling circuit that allowed us to achieve better resolution than what has been reported to date for 3 GS/s ADCs. The inherent total ionizing dose (TID) radiation tolerance of the SiGe fabrication process is utilized to achieve hardness to 2 Mrad(Si). The ADC output can be directly read out with an FPGA that is also used to host the designed ADC calibration algorithm that effectively cancels out mismatches between the time-interleaved pipeline ADC channels. The effective number of bits (ENOB) of this ADC, simulated as 11.0 bits, is a full 2 bits higher than what is reported for similar top-of-the-line commercially available devices and the simulated power consumption is also 60 to 70% lower compared to reported commercial developments.