Design of asynchronous 2-phase ternary encoding protocol using multiple-valued logic

Abstract

Due to a half transitions for data transfers comparing with conventional 4-phase signalings, level-encoded dual-rail (LEDR) has been widely used in on-chip asynchronous interconnects supporting a 2-phase handshake protocol. However, it inevitably requires 2N wires for N-bit data transfers to maintain delay-insensitive encoding. Encoder and decoder circuits that perform an asynchronous 2-phase handshake protocol with only N wires for N-bit data transfers are presented for on-chip global interconnects. Their fundamentals are based on a ternary encoding scheme, and the circuits are implemented using current-mode multiple-valued logics. In the simulation with 0.25 μm CMOS technology, the suggested circuits saves both latency and energy consumption over the wire length of 3 mm.