Design of Approximate Logarithmic Multipliers

Abstract

Lower power has been a main challenge for IC design. Approximate computing provides a new approach for low power design. Logarithmic multiplier (LM) is a kind of approximate multipliers in nature. In this paper, the design of both non-iterative and iterative approximate LMs (IALM) are studied to further reduce the power consumption and improve the performance. Non-iterative approximate LMs (ALM) that use three inexact mantissa adders are presented. The proposed IALMs use set-one adder in both mantissa adders during the iteration and they also use lower-part-or adders and approximate mirror adders for the final addition. The error analysis and simulation results are also provided. It is found that the proposed approximate LMs with appropriate number of inexact bits has achieved even higher accuracy and lower power consumption compared with the conventional LMs using exact units. To be exact, compared with conventional LMs with exact units, the normalized mean error distance (NMED) of 16-bit approximate LMs is decreased by up to 18% and the power-delay product (PDP) has a reduction of up to 37%. The proposed approximate LMs are also compared with previous approximate Booth multipliers. It is found that approximate LMs are more suitable for applications allowing large errors but require less power consumption, while approximate Booth multipliers fit for applications allowing larger power but require less errors.